In commonly owned U.S. patent application Ser. No. 839,883, filed Oct. 6, 1977 by one of us, Mario Bambara, jointly with Adriano Querze, there has been described a data processor dialoguing with a multiplicity of peripheral units with which the processor is able to exchange data in the presence of input/output instructions read out from a program memory. The macroinstructions stored in that memory (which also include transfer and branching instructions besides the aforementioned input/output instructions) are decoded in a control unit which establishes a subroutine on the basis of bit combinations of a current instruction, entered by the program memory in an associated register, and bit combinations of a forthcoming instruction present in the output of the memory but not yet loaded into the register. Each subroutine involves the readout of a number of microinstructions stored in another memory within the control unit itself.
Certain peripheral units (e.g. teletypewriters), when ready to transmit data to the processor, require an interruption of the program since their operating speed is slower than that of the processor. In the system of the prior Bambara et al application referred to, such program interruptions rank lower than an execution command emitted at the end of a microroutine as determined by a first priority coder within the control unit. A second priority coder in the control unit establishes an order of precedence among different peripheral units which may call for an interruption of the processor program. A subunit within the control unit prevents the occurrence of program interruptions at the conclusion of two immediately consecutive microroutines, thus requiring the extraction of at least one new macroinstruction from the corresponding memory between successive interruptions. A single peripheral unit, therefore, can occupy the processor for a limited time only.
An interface unit associated with a peripheral unit of the low-speed type has been described and claimed in commonly owned U.S. patent application Ser. No. 913,232 filed June 6, 1978 by Armando Consigli and Roberto Danna; the disclosure of that application is hereby incorporated by reference into the present application. That interface unit includes a sequential network which is switchable from a quiescent state (D) to a preparatory state (A) in response to the appearance of an input/output instruction addressing the associated peripheral unit. Via an intermediate state (B), attained in the absence of an overriding priority as determined by preferential circuitry such as the two priority coders disclosed in Bambara et al application Ser. No. 839,833, the network is switched to an active state (C) in response to a data-ready signal from the associated peripheral unit. A program-suspension request sent out in this active state by the interface unit elicits from the processor a confirmation signal which initiates the data transmission called for by the input/output instruction; the confirmation signal also returns the sequential network to its quiescent state (D).
Telecommunication systems of the type here envisaged may also include peripheral units operating at a higher speed so as not to require any sustained program interruption at the processor. Such peripheral units may include, for example, line detectors monitoring the activities of respective communication channels. Thus, a high-speed peripheral unit may be given direct access (DMA) to the central memory of the processor for transferring thereto a series of data words from its own store or receiving such data words therefrom.